1. Field
The present invention relates to non-volatile storage.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique For Non-Volatile Memory,” and in U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory;” both patents are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states, an erased state and a programmed state that correspond to data “1” and data “0.” Such a device is referred to as a binary device or as having single level memory cells.
A multi-state (or multi-level) flash memory cell is implemented by identifying more than two distinct allowed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits.
Non-volatile memory, like other integrated circuits, are susceptible to manufacturing defects. Some manufacturing defects are severe enough so that the integrated circuit never functions properly. These defects are typically found by testing during the manufacturing phase.
Other defects are minor or otherwise are not revealed until the integrated circuit has been used for a period of time. Some memory manufacturers attempt to identify the bad units as part of the manufacturing process. For example, some testing methods for flash memory include applying stress (temperature, voltage, cycling) to each block of memory in an effort to accelerate the failure of the blocks of memory that have defects which may cause failure after a period of operation. In some cases, the memory is programmed after or during the stress, the data programmed is read back, and the original data is compared with the data programmed and read back. If the difference is larger than some predefined threshold, the block is marked as bad and never used. A set of spare blocks exists to accommodate for bad blocks such that the total device capacity is within the product specification. A second scenario includes identifying a bad block when a programming or erasing operation fails. The failing block can be marked as bad and never used again.
None of the testing solutions described above can detect the situation where a programming process is successful, but the memory device later deteriorates (even without being accessed or only accessed for reading) and gradually loses its contents or the ability to read its contents.